Analog computing

Low Power circuit

 Objective: To design circuits and systems for readout, analog-to-digital conversion and feature extraction at aggressively low power (nanowatts) dissipation.

Approach: Wearable and implantable biomedical devices like smart bandages or smart sutures will need to operate on energy harvested from the environment. To meet the strict power requirements, we have made several innovations at the circuits and architecture level listed below.
  1. Suite of circuits operating at just 0.25V with nanowatt power dissipation such as operational amplifiers, asynchronous delta-sigma converters, Gm-C filters.
  2. Asynchronous event-driven digitizers such as slope-dependent asynchronous analog to digital converters
  3. Compressed sensing analog to information converters using edge triggered sampling.
  4. Direct analog to information converters using a unique input-feature correlated sampling approach that can acquire features directly from the analog signal without the need for nyquist-rate digitization or signal processing.
  5. Invented a time-mode translinear principle that utilizes transistor-free linear RC response to implement complex nonlinear functions such as analog multiplications and power laws.
  6. A visual saliency based neural network was implemented using time-mode analog circuits for the first time.
  7. Several VLSI potentiostats and impedance measurement circuitry on CMOS substrates. 
  8. Wireless power and data telemetry using inductive links at standard RFID frequencies. 

Sample publications:
  1. An adaptive resolution asynchronous ADC architecture for data compression in energy constrained sensing applications. IEEE Transactions on Circuits and Systems I: Regular Papers, 58(5), 921-934, 2011.
  2. Input-feature correlated asynchronous analog to information converter for ECG monitoring. IEEE transactions on biomedical circuits and systems, 5(5), 459-467, 2011.
  3. A 0.25-V 28-nW 58-dB dynamic range asynchronous delta sigma modulator in 130-nm digital CMOS process. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(5), 926-934, 2015.
  4. A computationally efficient visual saliency algorithm suitable for an analog CMOS implementation. Neural computation, 30(9), 2439-2471 2018.
  5. CMOS VLSI potentiostat for portable environmental sensing applications. IEEE sensors journal, 10(4), 820-821, 2010.
  6. Fully digital BPSK demodulator and multilevel LSK back telemetry for biomedical implant transceivers. IEEE Transactions on Circuits and Systems II: Express Briefs, 56(9), 714-718, 2009